1. Field of the Invention
The present invention relates to a simulator which can simulate a processor which executes pipeline processing of operation instructions, and a simulation method for a processor, using the simulator.
Recently, a processor in a multimedia market can execute real-time processing of video and audio of a dynamic scene as a result of improvement of operation performance. Further, a high-performance application can be formed by a personal computer, a portable terminal or the like.
However, when programming is performed by using a processor having such an operation performance, programming in a high-performance, complicated operation processing system is needed. Therefore, a simulator which can effectively debug a produced program is demanded.
2. Description of the Related Art
In the related art, a simulator does not exist which can simulate a processor which executes pipeline processing of operation instructions, executes operation processes in parallel in an order of inputting of the operation instructions (hereinafter, execution of the operation processes in the order of inputting of the operation instructions being referred to as xe2x80x98in-order executionxe2x80x99), and outputs results of the operation processes in an order of finish of the operation processes (hereinafter, outputting of the results of the operation processes in the order of finish of the operation processes being referred to as xe2x80x98out-of-order outputtingxe2x80x99).
Further, when simulation of an ordinary processor, which performs pipeline processing of operation instructions, and performs in-order execution and in-order outputting, is executed, it is not necessary for a simulator in the related art to perform a simulation exact in the pipeline processing, but, in many cases, a sufficient simulation result can be obtained as a result of a simulation being performed in which single instructions are executed one by one. The above-mentioned xe2x80x98in-order outputtingxe2x80x99 is outputting of results of the operation processes, the xe2x80x98in-order outputtingxe2x80x99 being opposed to the xe2x80x98out-of-order outputtingxe2x80x99. For example, the xe2x80x98in-order outputtingxe2x80x99 is outputting of results of the operation processes in the order of inputting of the operation instructions.
On the other hand, as described above, a simulator does not exist which can simulate a processor which executes the pipeline processing of the operation instructions, and performs the in-order execution and out-of-order outputting. However, when a processor model described by hardware description language (HDL) is used, because this processor model is a rigid circuit, precise simulation of the processor can be executed.
However, although a simulator in the related art can perform a simulation of an ordinary processor which performs the in-order execution and in-order outputting, the simulator in the related art cannot execute processing in which execution of a certain operation instruction finishes before (passes) previously started execution of another operation instruction due to a differing number of execution cycles between the certain operation instruction and the other operation instruction executed in parallel therewith, with regard to simulation of a processor which performs in-order execution and out-of-order outputting.
Further, in the case where a processor model described by hardware description language (HDL) is used, precise simulation of the processor can be performed because the processor model is a rigid circuit as mentioned above. However, the simulation speed is low and a significant time is required for debugging of the program.
Further, in the case where a processor model described by hardware description language (HDL) is used, execution of an operation instruction may pass previously started execution of another operation instruction due to the number of execution cycles of each operation instruction which is executed in parallel with execution of the other operation instructions. As a result, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program. Therefore, it is difficult to detect errors in the program unless a description for detecting errors is added.
An object of the present invention is to provide a simulator, in which execution of an operation instruction can pass previously started execution of another operation instruction due to in-order execution and out-of-order outputting, and a high-speed simulation and easy detection of errors in a program can be achieved as a result of detecting and indicating that execution of an operation instruction passes previously started execution of another operation instruction, a condition of waiting for enablement of an operation process occurring due to contention for a computing-unit resource, and an exceptional timing of outputting a result of an operation process occurring.
Another object of the present invention is to provide a simulation method using the above-described simulator.
A simulator, according to the present invention, can simulate a processor which performs pipeline processing of operation instructions, and performs operation processes in parallel, the number of the operation processes being larger than the number of the pipelines,
wherein the simulator simulates a passing operation in which a result of an operation process obtained from execution of the operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
The simulator according to the present invention can perform simulation of not only an ordinary processor which performs in-order execution and in-order outputting, but also a processor which performs in-order execution and out-of-order outputting, and can simulate the passing operation.
Further, because the simulator according to the present invention does not perform simulation using a rigid circuit (simulation model), it is possible to achieve high-speed simulation and high-speed program. debugging, in comparison to the case where simulation is executed by using a processor model described with the hardware description language (HDL).
The simulator may comprises passing-operation detecting means (corresponding to a passing-operation detecting portion 31 in an embodiment to be described later) for detecting occurrence of the passing operation.
In the simulator according to the present invention, similarly to the case where simulation is executed by using a processor model described with the hardware description language (HDL), the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program due to occurrence of the passing operation. As a result of the passing-operation detecting means detecting occurrence of the passing operation, indication of the occurrence of the passing operation can be performed, and thereby, errors in the program can be easily detected.
The simulator may further comprises passing-operation searching means (corresponding to a passing-operation marking portion 36 in the embodiment to be described later) for previously searching for an operation instruction, execution of which may cause the passing operation, before execution of the simulation,
wherein the passing-operation detecting means detects whether execution of the operation instruction, which has been found by the passing-operation searching means, actually passes previously started execution of another operation instruction.
Thus, the passing-operation detecting means detects whether execution of the operation instruction actually passes previously started execution of the operation instruction, only for the operation instructions which have been found by the passing-operation searching means. The passing-operation detecting means does not perform the detecting operation for the other operation instructions.
Accordingly, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
The simulator may comprise waiting-condition detecting means (corresponding to a pipeline-stall detecting portion 32 in the embodiment to be described later) for detecting a condition of waiting for enablement of an operation process, which condition occurs due to contention for a computing-unit resource.
In the simulator according to the present invention, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program, due to occurrence of the passing operation. As a result of the waiting-condition detecting means detecting the condition of waiting for enablement of the operation process, which condition occurs due to the contention for the computing-unit resource, indication of the condition of waiting for enablement of the operation process can be performed, and thereby, errors in the program can be easily detected.
The simulator may further comprise resource-contention searching means (corresponding to a resource-contention marking portion 37 in the embodiment to be described later) for previously searching for the operation instructions, execution of which results in the contention for the computing-unit resource, before execution of the simulation,
wherein the waiting-condition detecting means detects, whether the condition of waiting for enablement of the operation process occurs, as a result of determining whether contention occurs between the computing-unit resource which is used for execution of the operation instruction, which has been found by the resource-contention searching means, and the computing-unit resource which is used for previously started execution of another operation instruction.
Thus, the waiting-condition detecting means detects, whether the condition of waiting for enablement of the operation process occurs, as a result of determining whether contention occurs between the computing-unit resource which is used for execution of the operation instruction and the computing-unit resource which is used for execution of another operation instruction, execution of which is started previously, only for the operation instructions which have been found by the resource-contention searching means. The waiting-condition detecting means does not perform the waiting-condition detecting operation for the other operation instructions.
Accordingly, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
The simulator may comprise:
passing-operation detecting means for detecting occurrence of the passing operation;
waiting-condition detecting means for detecting a condition of waiting for enablement of an operation process, which condition occurs due to contention for a computing-unit resource;
resource memorizing means (corresponding to a resource using table 34 in the embodiment to be described later) for memorizing the computing-unit resources used for respective execution cycles of the operation process for each operation instruction; and
resource managing means (corresponding to a resource management table 35 in the embodiment to be described later) for managing which computing-unit resources are used for previously started execution of another operation instruction,
wherein the passing-operation detecting means and the waiting-condition detecting means detect occurrence of the passing operation and occurrence of the condition of waiting for enablement of the operation process, respectively, based on information obtained from the resource memorizing means and information obtained from the resource managing means.
Thus, the resource memorizing means previously memorizes the computing-unit resources used for respective execution cycles of the operation process for each operation instruction. As a result, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
The simulator may further comprise exceptional-outputting-timing detecting means (corresponding to an exceptional-outputting-timing detecting portion 33 in the embodiment to be described later) for detecting an exceptional outputting timing at which a result of the operation process is output, the exceptional outputting timing being different from a predetermined outputting timing.
In the simulator according to the present invention, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program, due to occurrence of the passing operation. As a result of the exceptional-outputting-timing detecting means detecting the exceptional outputting timing at which the result of the operation process is output, indication of the exceptional outputting timing can be performed, and thereby, errors in the program can be easily detected.
The simulator may further comprise exceptional-outputting-timing searching means for previously searching for the operation instruction, execution of which may result in outputting of the result of the operation process at the exceptional outputting timing, before execution of the simulation,
wherein the exceptional-outputting-timing detecting means detects whether the timing of outputting of the result of the operation process for the operation instruction which have been found by the exceptional-outputting-timing searching means is actually the exceptional outputting timing.
Thus, the exceptional-outputting-timing detecting means detects whether the timing of outputting of the result of the operation process for the operation instruction is actually the exceptional outputting timing, only for the operation instruction which has been found by the exceptional-outputting-timing searching means. The exceptional-outputting-timing detecting means does not perform the exceptional-outputting-timing detecting operation for the other operation instructions.
Accordingly, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
In a simulation method, according to the present invention, a processor is simulated which performs pipeline processing of operation instructions, starts operation processes in an order in which the operation instructions are input, executes the operation processes in parallel with execution of other operation instructions, and outputs results of the operation processes in an order in which the operation processes are finished,
wherein the method comprises the step of a) detecting a passing operation in which a result of an operation process obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction (corresponding to steps S1 through S10 in the embodiment to be described later).
In the simulation method according to the present invention, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program due to occurrence of the passing operation which occurs due to a difference in the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions. However, in the above-described method, the passing operation can be detected in the passing-operation detecting step a) and the passing operation can be indicated. As a result, detecting of errors in the program can be easily performed.
The simulation method may further comprise the step of b) previously searching for an operation instruction, execution of which may cause the passing operation (corresponding to steps S11 through S17 in the embodiment to be described later), before execution of the simulation,
wherein the step a) detects whether execution of the operation instructions, which have been found by the step b), actually passes previously started execution of another operation instruction.
Thus, in the passing-operation detecting step a), it is detected whether execution of the operation instruction actually passes previously started execution of the other operation instruction, only for the operation instruction which has been found in the operation-instruction searching step b). In the passing-operation detecting step a), the detecting operation is not performed for other operation instructions.
The simulation method may further comprises the step of b) detecting a condition of waiting for enablement of an operation process, which condition occurs due to contention for a computing-unit resource (corresponding to steps S21 through S32 in the embodiment described later).
In this simulation method, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program due to occurrence of the passing operation which occurs due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions. However, in the simulation method, the condition of waiting for enablement of the operation process can be detected in the waiting-condition detecting step b) and the condition of waiting can be indicated, which condition occurs due to contention for a computing-unit resource. Therefore, detecting of errors in the program can be easily performed.
The simulation method may further comprise the step of c) previously searching for operation instructions, execution of which may result in contention for the computing-unit resource, before execution of the simulation (corresponding to the steps S21 through S32 in the embodiment to be described later),
wherein the step b) detects, whether the condition of waiting for enablement of the operation process occurs, as a result of determining whether contention occurs between the computing-unit resource which is used for execution of the operation instruction, which has been found by the step c), and the computing-unit resource which is used for previously started execution of the operation instruction.
Thus, in the waiting-condition detecting step b), it is detected whether the condition of waiting for enablement of the operation process occurs, as a result of determining whether contention occurs between the computing-unit resource which is used for execution of the operation instruction and the computing-unit resource which is used for execution of the operation instruction, execution of which is started previously, only for the operation instruction which has been found by the resource-contention searching step c). In the waiting-condition detecting step b), the waiting-condition detecting operation is not performed for other operation instructions.
Accordingly, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
In the simulation method, in the passing-operation detecting step a) and the waiting-condition detecting step b), based on information obtained from resource memorizing means for memorizing the computing-unit resources used for respective execution cycles of the operation process for each operation instruction, and information obtained from resource managing means for managing as to which computing-unit resources are used for previously started execution of the operation instructions, occurrence of the passing operation and occurrence of the condition of waiting for enablement of the operation process are detected (corresponding to the steps S1 through S10, S21 through S32 in the embodiment to be described later), respectively.
Thus, the resource memorizing means previously memorizes the computing-unit resources used for respective execution cycles of the operation process for each operation instruction. As a result, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
The simulation method may further comprise the step of b) detecting an exceptional outputting timing at which a result of the operation process is output (corresponding to steps S41 through S45 in the embodiment to be described later), the exceptional outputting timing being different from a predetermined outputting timing.
In the simulation method according to the present invention, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program, due to occurrence of the passing operation which occurs due to a difference in the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions. However, in the above-described method, the exceptional outputting timing can be detected in the exceptional-outputting-timing detecting step b) and the exceptional-outputting timing can be indicated. As a result, detecting of errors in the program can be easily performed.
The simulation method may further comprise the step of c) previously searching for the operation instruction, execution of which may result in outputting of the result of the operation process at the exceptional outputting timing (corresponding to steps S41 through S45 in the embodiment described later), before execution of the simulation,
wherein the step b) detects whether the timing of outputting of the result of the operation process for the operation instruction which-has been found by the step c) is actually the exceptional outputting timing.
Thus, in the exceptional-outputting-timing detecting step b), it is detected whether the timing of outputting of the result of the operation process for the operation instruction is actually the exceptional outputting timing, only for the operation instructions which have been found in the exceptional-outputting-timing searching step c). In the exceptional-outputting-timing. detecting step b), the exceptional-outputting-timing detecting operation is not performed for other operation instructions.
Accordingly, it is possible to achieve a high-speed simulation and high-efficiency program debugging.
A computer readable recording medium, according to the present invention, stores a program for causing a computer to perform simulation of a processor which performs pipeline processing of operation instructions,
the program causing the computer to simulate a passing operation in which a result of the operation process obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
The program may cause the computer to execute the steps of:
a) detecting occurrence of the passing operation (corresponding to the steps S1 through S10 in the embodiment described later);
b) previously searching for an operation instruction, execution of which may cause the passing operation, before execution of the simulation (corresponding to the steps S11 through S17);
c) detecting a condition of waiting for enablement of an operation process (corresponding to the steps S21 through S32 in the embodiment to be described later), which condition occurs due to contention for a computing-unit resource:
d) previously searching for an operation instruction, execution of which may result in the contention for the computing-unit resource, before execution of the simulation (corresponding to the steps S21 through S32 in the embodiment to be described later);
e) detecting an exceptional outputting timing at which a result of the operation process is output (corresponding to the steps S41 through S45 in the embodiment to be described later), the exceptional outputting timing being different from a predetermined outputting timing; and
f) previously searching for an operation instruction, execution of which may result in outputting of the result of the operation process at the exceptional outputting timing, before execution of the simulation (corresponding to the steps S41 through S45 in the embodiment to be described later).
In the simulation performed by the computer in accordance with the program, simulation of not only an ordinary processor which performs in-order execution and in-order outputting, but also a processor which performs in-order execution and out-of-order outputting can be performed, and the passing operation can be simulated.
Further, in the simulation performed by the computer in accordance with the program, because a simulation is not performed using a rigid circuit (processor model), it is possible to achieve a high-speed simulation and high-speed program debugging, in comparison to the case where simulation is executed by using the processor model described with the hardware description language (HDL).
Other objects and further features of the present invention will become more apparent from the following detailed descriptions when read in conjunction with the accompanying drawings.